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First, in full output handshake, the port C lines are outputs whenever STRA is at its active level regardless of the data direction register bits. This potentially conflicts with any external device trying to drive port C unless that external device has an open-drain type output driver. Second, the value returned on reads of port C is the state of the outputs of an internal port C output latch regardless of the states of the data direction register bits, so that the data written for output handshake can be read even if the pins are in a three-state condition.

It has to be low prior to data transactions and must stay low for the duration of the transaction. The SS line on the master must be tied high. If it goes low, a mode fault error flag (MODF) is set in the serial peripheral status register (SPSR). The SS pin can be selected to be a general-purpose output by writing a one in bit 5 of the port D data direction register, thus disabling the mode fault circuit. The other three SPI lines are dedicated to the SPI whenever the SPI is on. SCK CYCLE # (FOR REFERENCE) 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT (CPHA = 0) DATA OUT MSB 6 5 4 3 2 1 LSB SAMPLE INPUT (CPHA = 1) DATA OUT MSB 6 5 4 3 2 1 LSB SS (TO SLAVE) SPI TRANSFER FORMAT Figure 6-1 Data Clock Timing Diagram When CPHA = 0, the shift clock is the OR of SS with SCK.

After a data byte is shifted, the SPIF flag of the SPSR is set. MSB INTERNAL MCU SYSTEM CLOCK LSB 8-BIT SHIFT REGISTER READ DATA BUFFER DIVIDER ÷2 ÷4 ÷16 ÷32 CLOCK S M MISO PD2 M S MOSI PD3 PIN CONTROL LOGIC SPI CLOCK (MSTR = 1) SELECT S M SPR1 SPR0 CLOCK LOGIC SCK PD4 MODF SPIF WCOL SPI CONTROL MSTR SPE SPIE 8 SPI STATUS (SPSR) SPIE SPE DWOM MSTR CPHA CPOL SPR1 SPR0 SPI INTERRUPT MSTR SPE DWOM SS PD5 SPI CONTROL (SPCR) SPI BLOCK DIAGRAM Figure 6-2 Serial Peripheral Interface Block Diagram In the master mode, the SCK pin is an output.

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